1. Field of the Invention
The present invention generally relates to noise problems at the input pads of integrated circuits. More particularly, this invention relates to a circuit and a method for eliminating negative voltage noise effects on multi-function input/output pads.
2. Description of the Prior Art
FIG. 1a shows a prior art input/output (I/O) pad of an integrated circuit. The I/O pad 110 feeds into two transfer gates, N1 (130) and N2 (170). In test mode, the Test Mode line 120 is driven to a HIGH, VDD level, which turns ON the transfer gate N1 (130). This action connects the pad 110 to some internal reference signal. This allows the reference signal to be controlled by the external pad 110 during test mode. During Normal mode, the Test Mode signal 150 or 120 will be low or inactive. The inverter 160 will produce a high level at node 161. This is the Normal mode signal, which activates transfer device N2 (170) during Normal mode. During normal mode operation, the pad 110 is connected to the normal mode circuit 180. In addition, during normal mode, the Test mode signal 120 is low or inactive and transfer device N1 (130) is OFF. This disconnects the path from the pad 110 to the internal reference signal node 140.
FIG. 1b shows a prior art timing diagram 115 for a variable signal, which is applied, to the pad 110 in FIG. 1a. The signal shown in FIG. 1b, has an under shoot 125 where the voltage falls to −1 Volt or below. During this time device N1 is not OFF, and the pad is connected to the test mode internal reference signal node 140 in FIG. 1a. This will cause the chip to fail.
U.S. Pat. No. 6,812,595 B2 (Marino) describes a protection circuit and method for reducing noise received at a circuit operating on a voltage reference supply. The circuit includes a reference voltage source and at least one circuit which are connected together via a switch. A memory element which is attached to the switch is used to remember the previously stored reference voltage. Noise produced by a power element cannot disturb the circuit since the proper reference voltage has been previously stored in the memory element.
U.S. Pat. No. 6,826,025 (Singh, et al.) discloses an integrated circuit having either or both ESD and noise suppression devices that use the inherent resistance in the substrate as an ESD trigger and/or part of the noise suppression.
U.S. Pat. No. 4,893,029 (Matsuo, et al.) describes a semiconductor integrated circuit which has an input circuit, an internal circuit, and an output circuit. These circuits are all formed on a single chip and are connected to common power source lines. The input circuit includes an ordinary Schmitt trigger circuit, and an FET. The FET is turned ON for a predetermined period of time by a control signal when the potentials of the power source lines (positive power source line and an earth line) are caused to fluctuate as a result of the internal circuit or the output circuit operating. Because of this, the level to detect the rising of the input signal is set to a level higher than the ordinary level for the period of time during which the potentials of the power source lines fluctuate.